DAC 2019

ANSYS Multiphysics Enables Silicon Success

The new era of semiconductors will enable transformational products for AI, 5G, automotive, networking, cloud and edge compute applications. Ubiquitous connectivity, low latency and faster data rates will result in more data being generated at the edge, more data being transported across the network and more data being processed both at the edge and in the cloud. These applications will rely on advanced, low-power FinFET designs and state-of-the-art 3D-IC packaging technologies to deliver the required power, performance, area and reliability. Multiphysics analysis is critical for these cutting edge electronics systems to work reliably throughout their lifetimes. ANSYS empowers customers with big data analytics, elastic compute scalability and multiphysics simulations to simultaneously solve power, thermal, variability, timing, electromagnetics and reliability challenges across the spectrum of chip, package and system to ensure first-time silicon and system success.

Sign up for our ANSYS Workshop and Meet the Expert sessions to learn about industry best practices for leveraging multiphysics simulations to enable silicon-to-system success.

Recommended presentations for:

Workshops

Leading industry experts will share their best practices using ANSYS solutions on topics that are critical to their design and methodology.

1)	Addressing Voltage Variability & Timing Challenges in Advanced FinFET Designs

Addressing Voltage Variability & Timing Challenges in Advanced FinFET Designs

Design for Power Efficiency: Early RTL methodology for Chips and IPs

Achieve Early Power Efficiency at RTL: AI, ADAS, Mobile Designs and More

Accelerate SoC power signoff and make your data actionable

Power Integrity Signoff for Complex SoCs with RedHawk-SC

Multiphysics reliability signoff for chip, package and system

Multiphysics Signoff for Chip, Package and System

Meet the Experts


  • Power Noise and Reliability Signoff for Analog-Mixed Signal Designs

    Power Noise and Reliability Signoff for Analog-Mixed Signal Designs

  • 2.5D/3D-IC Analysis and Chip-Package-System Co-Design

    2.5D/3D-IC Analysis and Chip-Package-System Co-Design

  • Achieving Early RTL-Driven Chip and IP Power Efficiency - Best Practices

    Achieving Early RTL-Driven Chip and IP Power Efficiency - Best Practices

  • Next Generation SoC Power Noise Reliability Signoff

    Timing and Voltage Variability

  • De-Risking High Speed Designs from Electromagnetic Crosstalk Issues

    De-Risking High Speed Designs from Electromagnetic Crosstalk Issues

  • Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

    Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

  • Design Innovation Through Multiphysics Simulation

    Design Innovation Through Multiphysics Simulation

SoC Physical Designer

ANSYS recommends the following presentations for SoC physical designers

Workshops
Meet the Experts
Mon: 10-12 Track 1: Addressing Voltage Variability & Timing Challenges in Advanced FinFET Designs Mon: 1-2 De-Risking High Speed Designs from Electromagnetic Crosstalk Issues
Tue: 10-12 Track 3: Power Integrity Signoff for Complex SoCs with RedHawk-SC Tue: 4-5 2.5D/3D-IC Analysis and Chip-Package-System Co-Design
Tue: 2-4 Track 4: Multiphysics Signoff for Chip, Package and System Mon: 12-1 Timing and Voltage Variability
    Tue: 12-1
Wed: 2-3
Design Innovation Through Multiphysics Simulation
    Wed: 1-2 Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

Analog Mixed-Signal / IP Designer

Workshops
Meet the Experts
Mon: 10-12 Track 1: Addressing Voltage Variability & Timing Challenges in Advanced FinFET Designs Mon: 1-2 De-Risking High Speed Designs from Electromagnetic Crosstalk Issues
Tue: 2-4 Track 4: Multiphysics Signoff for Chip, Package and System Tue: 1-2 Power Noise and Reliability Signoff for Analog-Mixed Signal Designs
    Tue: 4-5 2.5D/3D-IC Analysis and Chip-Package-System Co-Design
    Tue: 12-1
Wed: 2-3
Design Innovation Through Multiphysics Simulation
    Wed: 1-2 Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

Chip-Package-System Designer

Workshops
Meet the Experts
Mon: 10-12 Track 1: Addressing Voltage Variability & Timing Challenges in Advanced FinFET Designs Mon: 1-2 De-Risking High Speed Designs from Electromagnetic Crosstalk Issues
Tue: 2-4 Track 4: Multiphysics Signoff for Chip, Package and System Tue: 4-5 2.5D/3D-IC Analysis and Chip-Package-System Co-Design
    Tue: 12-1
Wed: 2-3
Design Innovation Through Multiphysics Simulation

RTL Designer

Workshops
Meet the Experts
Mon: 2-4 Track 2: Achieve Early Power Efficiency at RTL: AI, ADAS, Mobile Designs and More Mon: 4-5 Achieving Early RTL-Driven Chip and IP Power Efficiency - Best Practices

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