ANSYS Chip-Package (and System) Co-Simulation Workshop


11:00 AM - 2:00 PM (PST)

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2645 Zanker Road
San Jose, CA 95134

Verly Flores

The performance of an electronic system largely depends on its immunity from power, signal and thermal noise. Since the components, chip, package and system are done by different teams, and often from different companies, they end up being defined for pre-defined margins and by teams, for all practical purposes in isolation.

Join us for this technical session where you will learn how to integrate the chip and package extraction using a more streamlined flow. Learn how to export the die extraction (lumped/distributed) and combine with the rest of the system in ANSYS SIwave and perform full system PDN extraction.

This seminar will include hands-on exercises to demonstrate how to:

  • Hook up a Chip Power Model (CPM) onto package layout in SIwave
    • Assign ports/current/voltage sources depending on AC or DC analysis
  • Perform a High-Frequency Power Integrity simulation on a chip+pkg+pcb example
    • Extract lumped parasitics for the power and ground pins of the device using SIwave-CPA 
    • Perform chip-package -system full PDN Power Integrity (AC & Transient) simulation in CMA 

Hands-on session limits registration to 12 attendees. Please register today to reserve your spot. Lunch will be provided.