DAC 2017

Accelerating Multiphysics Multi-Scale Signoff

Next generation automotive, mobile and high-performance computing systems demand the use of 16/7nm SoCs that are bigger, faster and more complex. For these systems and SoCs, the margins are smaller, the schedules are tighter and the costs are higher. So faster convergence with exhaustive coverage is imperative for on-time SoC and system success. Traditional margin-driven, silo-based design approaches of the chip, package and board lead to sub-optimal designs. ANSYS solutions deliver a multiphysics, multiscale, big data simulation platform that simultaneously solves for thermal properties, reliability, power-timing and performance across the chip-package-system spectrum to accelerate your product success.

Recommended presentations for:

Workshops

Participate in the ANSYS industry workshops at this year's conference. In these workshops, industry experts from leading semiconductor companies will share their best practices and methodologies across a range of topics.

Workshop 1

Multiphysics Optimization & Signoff
for Chip, Package & System

Workshop 1

Multiphysics Reliability Signoff for
Mission Critical Applications

Workshop 1

Next Generation SoC
Power Signoff

Workshop 1

Early RTL-driven Chip &
System Power Flows

Best Practices Seminars


  • Production Proven Workflows for ADAS, Mobile and HPC Designs

    Production Proven
    Workflows for ADAS,
    Mobile and HPC
    Designs

  • Next Generation SoC Power Noise Reliability Signoff

    Next Generation SoC
    Power Noise
    Reliability Signoff

  • Thermal, EM and ESD Reliability Signoff for Advanced Designs

    Thermal, EM and ESD
    Reliability Signoff for
    Advanced Designs

  • Analog and Mixed-Signal IP Power Noise Reliability Signoff

    Analog and Mixed-Signal
    IP Power Noise
    Reliability Signoff

  • Bridging the Gap of Chip, Package & System

    Bridging the Gap of
    Chip, Package
    & System

  • RTL-driven System Power Profiling & Reduction

    RTL-driven System
    Power Profiling &
    Reduction

  • Variability-aware and SPICE-accurate Timing Closure

    Variability-aware and
    SPICE-accurate
    Timing Closure

Recommended presentations for the SoC Physical Designer


Workshops Best Practices
Mon: 10-12 Multiphysics Optimization & Sign-off for Chip, Package & System Mon: 1-2
Tues: 4-5
Wed: 1-2
Production Proven workflows for ADAS, Mobile and HPC Designs
Mon: 2-4 Multiphysics Reliability Signoff for Mission Critical Applications Mon: 4-5
Tues: 1-2
Wed: 10-11
Next Generation SoC Power Noise Reliability Sign-off
Tue: 10-12 Next Generation SoC Power Signoff Mon: 4-5
Tues: 1-2
Wed: 11-12
Thermal, EM and ESD Reliability Signoff for Advanced Chip Designs
    Mon: 1-2
Tues: 3-4
Wed: 11-12
Variability-aware and SPICE-accurate Timing Closure

Recommended presentations for the Analog Mixed-Signal / IP Designer


Workshops Best Practices
Mon: 10-12 Multiphysics Optimization & Signoff for Chip, Package & System Mon: 1-2
Tues: 4-5
Wed: 1-2
Production Proven Workflows for ADAS, Mobile and HPC Designs
Mon: 2-4 Multiphysics Reliability Signoff for Mission Critical Applications Mon: 4-5
Tues: 1-2
Wed: 11-12
Thermal, EM and ESD Reliability Signoff for Advanced Chip Designs
    Mon: 3-4
Tues: 4-5
Wed: 1-2
Analog and Mixed-Signal IP Power Noise Reliability Signoff
    Mon: 1-2
Tues: 3-4
Wed: 11-12
Variability-aware and SPICE-accurate Timing Closure

Recommended presentations for the Chip-Package-System Designer


Workshops Best Practices
Mon: 10-12 Multiphysics Optimization & Signoff for Chip, Package & System Mon: 1-2
Tues: 4-5
Wed: 1-2
Production Proven Workflows for ADAS, Mobile and HPC Designs
Mon: 2-4 Multiphysics Reliability Signoff for Mission Critical Applications Mon: 4-5
Tues: 1-2
Wed: 11-12
Thermal, EM and ESD Reliability Signoff for Advanced Chip Designs
    Mon: 2-3
Tues: 2-3
Bridging the Gap of Chip, Package & System

Recommended presentations for the RTL Designer


Workshops Best Practices
Tue: 2-4 Early RTL-driven Chip & System Power Flows Mon: 11-12
Tues: 11-12
Wed: 10-11
RTL-driven System Power Profiling & Reduction - Best Practices

From the above sessions you will learn:

Next Generation SoC Power Signoff
The growing interdependency of various multiphysics attributes such as timing, power and thermal properties in sub-16nm designs poses significant design challenges. Existing solutions are not designed to solve such a multidimensional optimization problem. These solutions have limited simulation coverage that fail to reveal potential design weaknesses that lead to field failures. Leveraging ANSYS SeaScape's big data architecture for power signoff gives you elastic scalability to solve billion-plus instance designs within a few hours. It lets you perform rapid design iterations across multiple scenarios and operating conditions. Using big data analytics, it prioritizes design issues based on multiple competing design attributes. Also, ANSYS SeaScape's machine learning technology platform enables a wide range of applications, such as identifying missed systematic design weaknesses and automating time-consuming rigorous manual procedures. The machine learning technology platform does this by aggregating key insights across different designs using continuing and prior simulation and design data. This platform has been used in production workflows to reduce time to market efforts and accelerate convergence for next-generation designs.

Multiphysics Signoff for Chip-Package-System
Existing margin-driven, silo-based design approaches for the chip, package and board severely limit your ability to globally optimize these systems without overdesigning. The economics of sub-16nm SoCs requires the judicious use of resources across the chip, package and board. For example, for systems operating in the sub-500 mV range, existing single physics solutions will lead to significant overdesign. This affects cost and schedule and does not guarantee performance. Only ANSYS offers comprehensive chip-package-system (CPS) workflows for solving thermal, power, signal, EM, ESD, EMI and EMC issues for chip-aware system and system-aware chip signoff.

FinFET Thermal and Reliability Signoff
For 16/7nm SoCs, increased functionality and higher current densities cause localized self-heating of devices and Joule heating of wires, leading to a large temperature variation across the chip based on different modes of operation. Higher temperature, higher current and higher resistances are pushing the limits for electromigration (EM) and electrostatic discharge (ESD) failures on-chip. For certain mission-critical applications, such as air-bag deployment devices, the ambient temperature of the chip can also affect the transient behavior. In addition, advanced 2.5-D/3-D and wafer-level packaging technologies are bringing the die and wafer together, creating more thermal hot spots that will impact both the chip- and system-level EM and ESD. These packaging technologies can also increase the chance of thermal-induced stress that can lead to warping and contact separation, causing long term reliability issues that will ultimately render the product useless. ANSYS' chip-package-system (CPS) thermal solutions offer comprehensive chip-level thermal analysis and chip-aware, system-level thermal analysis to achieve thermal integrity and power-thermal convergence across the chip, package and board.

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