3DIC design has plenty of technical challenges, from design setup to tape-out, due to its complexity. In particular, seamlessly connecting a power delivery network (PDN) from a voltage regulator module (VRM) through a board, package and interposer to a chip directly impacts the 3DIC performance. A minor error can cause significant performance degradation. Only a fully integrated power integrity analysis solution can predict potential power noise and prevent unexpected performance issues. However, in reality, all components of a 3DIC are implemented in silos, and conventional co-analysis methodologies do not cater to this silo approach.
Join us for this webinar in which we will address the technical challenges of 3DIC power integrity analysis and propose a comprehensive CPS-integrated co-analysis solution based on ANSYS products. The proposed solution will include a chip model creation encompassing multiple dies; PDN parasitic extraction of the interposer, package, and board; seamless connection of all PDN channels; and AC and transient analyses.