cps-co-design

Chip-Package-System Co-design and Co-analysis Solutions for 3DICs

January 30, 2018

1:30 PM - 5:30 PM (PST)

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Venue:
Hyatt Regency
5101 Great America Parkway
Santa Clara, CA 95054
USA

Bayshore Room  

Contact:
Nilva Fuller
nilva.fuller@ansys.com

Advanced packaging technologies will be the key driver of heterogeneous integrations in next generation HPC, Cloud computing, Automotive and IoT electronics systems to achieve extreme performance, high system bandwidth, low power and low cost. The internet of everything – the reality of tomorrow – will generate huge amounts of data to be processed and stored and the ability to handle such large volumes of data will be threatened by limited system bandwidth between the traditionally packaged processor and the memory that is integrated into the system. Hence advanced 3DIC packaging technology that includes 3D integration and its enabling processes and platforms (through silicon vias (TSVs), die and wafer stacking, system-in-package (SiP), package-on-package (PoP), advanced wafer-level packages (WLP), and interposer integration) that leverages the third dimension for scaling will be a popular choice. Short interconnection paths enabled by TSVs between stacked chips will lead to higher performance, lower power, and smaller form factor. It is indeed a very promising technology, however, fraught with many challenges due to its complexity.

In this workshop, ANSYS will showcase a comprehensive 3DIC Chip-Package-System (CPS) solution for power, signal and thermal integrity signoff that is seamless and easy to set up. Leading industry experts from Xilinx and Samsung Electronics will share relevant case studies on the need for enabling CPS co-design and co-analysis solutions to root cause electronics system failures. Don’t miss this exciting opportunity to meet industry experts and learn about designing robust 3DIC electronics systems for next generation applications. 

A DesignCon pass is not required, but pre-registration is necessary in order to attend the event. Register today to reserve your spot.

Agenda

Time Topic
1:30 – 1:35  Welcome and Introduction
1:35 – 2:15 The Need for Chip-Package-System Co-design and Co-analysis for 3DICs
2:15 – 3:00 Industry Case Study by Xilinx
Concurrent  3DIC Power Supply Analysis for Xilinx SerDes Interface 
3:00 – 3:15 Break
3:15 – 3:55 Addressing Challenges and Solutions for 3DIC Signal Integrity
3:55 - 4:30 Industry Case Study by Samsung Electronics
Root-cause Analysis and Resolution of Mobile System Failure through 
Chip-Package-System Co-Simulation
4:30 – 5:30  Reception and Raffle