Getting on Board with Vias

By Rick Rabinovich, Signal, Integrity Hardware Architecture, IXIA, Calabasas, USA

It's not uncommon to have a design fail in the field due to signal integrity issues even though simulation shows it should work perfectly because the as-manufactured product differs from the design definition. To avoid this problem, the signal integrity engineer needs to understand what will actually be delivered and use simulation to verify that the frequency- and time-domain performance will meet the design requirements. Simulation can be used to address the question of how differences between as-designed and as-built vias might degrade time- and frequency-domain performance of printed circuit boards (PCBs).

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CAD solid via

via electric field

Most of the differential electric field is distributed along the external surface of the via with minimum internal field strength.

To reduce complexity to manageable levels, electronic products are nearly always initially designed based on a series of simplifying assumptions, such as that its geometry will match the perfect shapes defined in the CAD system. Of course, the manufacturing process cannot build these perfect shapes, at least not at a price customers are willing to pay, and the product still needs to meet performance requirements. Electronics theory is not much help because it addresses only the perfect world defined in a CAD system. Physical experiments can answer the question, but only at a very high cost and with the lead time required to build the product to varying specifications. Simulation, on the other hand, provides a practical solution by modeling both the perfect world and an unlimited number of more realistic scenarios to determine whether or not performance will meet expectations.

For example, PCB vias that interconnect traces between signal layers are almost always defined in a computer-aided design (CAD) system as solid cylinders. When the PCB is simulated, the simulation model typically matches the design definition. However, in the real world, PCB manufacturers generally build vias by drilling a hole through the PCB and electroplating the hole with copper deposited to a thickness of between 1 and 2 mils. The center of the hole may be empty or it may contain filling paste, copper debris or a combination of all of these. This raises a significant signal-integrity concern — does the conflict between the design definition and the manufacturing process have a negative impact on the performance of the product?

solid via
Simulation 1 frequency- and time-domain performance of a solid via
air-filled via
Simulation 2 frequency- and time-domain performance of an air-filled via
past-filled via
Simulation 3 frequency- and time-domain performance of a paste-filled via
enlarged diameter via
Simulation 4 frequency- and time-domain performance of an enlarged-diameter via

The reason why engineers are not usually concerned about whether a via is a solid cylinder or a hollow barrel is the assumption that the skin effect will cause high-frequency current to flow in the outer surface of the conductor regardless of the conductor's geometry. The skin depth equation can be used to quantify the decrease in current density from the surface to the center of the conductor. This equation shows that for a frequency of 500 MHz, 99 percent of the current flows within less than 0.6 mil from the outer surface. This is well below the minimum 1 mil copper plating thickness specified in most board manufacturing processes. Does this mean that a PCB with vias shaped like hollow barrels will provide the same performance as a PCB with vias shaped like solid cylinders?

The question is complicated by the fact that PCB manufacturers frequently cut out a via with a drill bit whose diameter is 1 to 3 mils larger than the specified finished hole size. Then the manufacturer plates the inner walls of the hole with 1 to 2 mils of conductive material, leaving the inside empty or filled with some nonconductive material. Due to imperfections in the plating process, some conductive material plating residue may even remain in the hole. For example, if a 10 mil via is specified, the result will be a barrel with an 11 to 13 mil outside diameter barrel and a 10 mil inside diameter.

"Whether the hole is empty, copper-filled or filled with paste, the frequency and time domain performance remain the same as long as the outer wall diameter remains constant."

It's logical to assume that a larger diameter barrel will increase the parasitic capacitance between the barrel and the adjacent power planes due to increased proximity between the outer barrel wall and the adjacent power plane edges. The amount of signal degradation is a function of the via structure and the characteristics of the surrounding area, such as the number and proximity of power planes, so it can't be quantified as a generic number or defined by rule of thumb. An impedance degradation will cause increased return losses, which reduce the bandwidth of the channel, increase the rise time and cause closure of the eye.

Ixia engineers used ANSYS HFSS to simulate a PCB with four different via structures:

  • Simulation 1: 10-mil outer diameter, solid cylinder matching the typical design specification
  • Simulation 2: 10-mil outer diameter, 8-mil inner diameter barrel filled with air
  • Simulation 3: 10-mil outer diameter, 8-mil inner diameter barrel filled with paste
  • Simulation 4: 12-mil outer diameter, 10-mil inner diameter barrel filled with air. This represents the typical as-manufactured via when the design is specified as in simulation 1.

Simulations 1, 2 and 3 deliver similar results in terms of insertion loss

Simulations 1, 2 and 3 deliver similar results in terms of insertion loss, return loss and differential impedance as expected from skin effect theory. Simulation 4 has a higher insertion loss, lower return loss and lower differential impedance.

All four simulations were analyzed at 12.89 GHz, the Nyquist frequency of a 25 Gb/s Ethernet differential signal. These examples used a multilayer PCB structure consisting of a differential stripline pair located on layer 26, sandwiched between ground planes on layers 25 and 27. A differential port P1 comprising lumped ports was located between the pads and ground on the top layer of the PCB. The pads were placed on top of the vias (via-in-pad). The second differential port, P2, was a waveport located between the differential striplines in layer 26 and the adjacent ground planes.

The simulation results shown in the table indicate that simulations 1, 2 and 3 deliver similar results in terms of insertion loss, return loss and differential impedance as expected from skin effect theory. Simulations 1, 2 and 3 also show similar differential impedance, ranging from 92.535 to 92.708 at their lowest point. On the other hand, simulation 4 has a higher insertion loss, lower return loss and lower differential impedance due to increased parasitic capacitance caused by the decrease in spacing between the barrel walls and the edge of the power planes. These results are especially noteworthy considering that simulation 4 best represents actual manufacturing practices.

In summary, whether the hole is empty, copper-filled or filled with paste, the frequency and time-domain performance remain the same as long as the outer wall diameter remains constant. This is because 99 percent of the current flows through the outer surface of the barrel due to the skin effect. However, the signal integrity engineer needs to be aware that the common case where the as-built via diameter ends up 1 to 3 mils larger than the diameter specified may result in a significant performance degradation. The signal integrity engineer needs to consult with the PCB manufacturer to understand its manufacturing process. Simulation then can be used to investigate the performance of the as-manufactured design from a signal integrity standpoint before building the board.

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