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Presentation

Bi-directionally Coupled Full-wave EM to Thermal Stress Simulation

From Dimensions of Electronic Design Seminar, 2012: The design of high-performance RF/microwave systems and components often requires consideration of operating in a real-world multi-physics environment. Understanding the interaction between multiple coupled physics is essential for an accurate system analysis. With ANSYS HFSS 15.0, we offer a comprehensive solution capable of performing bi-directional coupled analysis between EM, thermal, structural mechanics and fluid flow. This presentation will demonstrate the new capability through several examples, where it is important to consider not only individual physics, but also the coupled interaction. A typical design flow is demonstrated, using HFSS to calculate RF losses, ANSYS Mechanical for thermal and structural analysis, and ANSYS Fluent or ANSYS Icepack to analyze fluid flow. Data exchange between physics is automated using the intuitive design flow of ANSYS Workbench. Providing both thermal and mesh deformation feedback into HFSS where the electrical performance can be reanalyzed to predict real-world performance.

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Presentation

SIwave for Power Integrity

From Dimensions of Electronic Design Seminar, 2012: Advanced power integrity simulations allow engineers to understand how changes in their designs affect device operation and power plane noise. In this presentation we exhibit a chip-package-board simulation method using ANSYS SIwave and ANSYS Designer SI with Apache Chip Power Models (CPM) from RedHawk. The package is modeled using static S-parameters and the board is extracted in SIwave. Plane impedance, board resonances, and simultaneous switching noise simulations provide insight into the performance of the power distribution network and we optimize the decoupling capacitor solution on the board using ANSYS PI Advisor. The presentation also introduces some of the new features of SIwave 7 as they relate to power integrity simulation.

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Presentation

Serial Interconnect Design from Layout to PCIe Specifications

From Dimensions of Electronic Design Seminar, 2012: Post layout validation is a common practice prior to certifying a design. Engineers typically simulate the physical architectures, create electromagnetic-based models, and apply time domain signaling in conjunction with these models. ANSYS has streamlined this process for signal integrity engineers with the use of two products, ANSYS Designer SI and ANSYS SIwave. SIwave with Alinks now embedded, allows users to directly import their layout geometry ready to solve in the SIwave hybrid engine. Critical areas of the geometry can be simulated with additional 3D accuracy by simply identifying the region followed by rigorous ANSYS HFSS analysis. After the physical channel model has been extracted a simple step brings the entire channel into Designer SI. Designer SI, the time domain transient solver is used to simulate time domain channel response driven by transmitter, receiver models such as IBIS or IBIS AMI. User-defined outputs (UDOs) allow the user to quickly view time specification driven measurements such as pass/fail eye characteristics to verify design validity.

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Presentation

Optimal Phased Array Modeling Using Domain Decomposition

From Dimensions of Electronic Design Seminar, 2012: New computational techniques will be introduced for enhancing the modeling capabilities of finite phased antenna arrays. Creating tapered or sparse finite array element configurations is a snap in ANSYS HFSS 15.0. Solve times may be reduced by several orders of magnitude when only a subset of scan vectors is required or sped up significantly for an array desiring full scan information. Pattern accuracy is enhanced with a new numerical absorbing boundary that is effective at all scan angles. Comparisons of finite array DDM and explicit models will be shown. Finally, guidance will be given about optimal hardware/software setup to tackle phased array modeling.

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Presentation

Large Scale Microwave EM from Layout

From Dimensions of Electronic Design Seminar, 2012: This presentation demonstrates how large microwave circuits can be created and simulated using the HFSS for ECAD layout interface. This new user interface combines a layout editor-based drawing tool with a new streamlined, single click port creation capability, as well as automated air region creation and boundary assignments. We will show how these new capabilities substantially decrease the amount of effort required to create extremely large and highly complex microwave circuits. Additionally, we will showcase how this new design flow is further enhanced by allowing users to easily and quickly include lumped elements or S-parameter models in an HFSS simulation. Since large scale microwave circuits often include large numbers of vias and/or bondwires, we will also discuss how the new release of HFSS can be used to efficiently handle high via and/or bondwire counts.

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Presentation

Advanced Signal Integrity with a Chip-Package-System Methodology

From Dimensions of Electronic Design Seminar, 2012: Signal and Power Integrity and EMI/ESD are challenging areas in electronics design and can be the most limiting factor in successful product launches. With exceptionally short design cycle life times for today’s modern electronics, system simulation driven product development has become more important than ever. With the release ANSYS R14.5 there is a new set of advanced rigorous simulation techniques implemented for simulating SI/PI and ESD/EMI design challenges. In this presentation we will present a detailed overview of ANSYS SIwave 7 with a chip-package-system (CPS) flow. It will also include an overview of the new user interface for ANSYS AnsoftLinks, for automated 3D simulation using ANSYS HFSS, and newly integrated prism-based Apache PSI full-wave solver. New capabilities and improvements in ANSYS DesignerSI 8 and HFSS 15.0 for signal and power integrity and EMI/ESD will also be shown.

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Presentation

DDR Compliance

From Dimensions of Electronic Design Seminar, 2012: Predicting today’s memory interfaces is of great importance for many companies that design modern electronics systems. The most common need is an automated and accurate physical extraction of memory channel components and overall system compliance verification of memory interface modules. Using ANSYS SIwave and ANSYS DesignerSI automated capabilities, engineers are enabled to simulate physical behavior of memory channels and verify performance against strict DDR3 electrical standards. ANSYS User Defined Solutions allow calculations and post-processing of raw transient simulation data, which creates User Defined Documents containing detailed information about AC data timing calculations such as setup and hold times, eye diagrams due to the strobe crossing, de-rating including a support for non-ideal voltages for every bit-by-bit falling and rising transition edge.

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Presentation

Ultra-Low-Power Design Methodology using RTL2Gate Flow

From Dimensions of Electronic Design Seminar, 2012: Power budgeting and power delivery integrity are key targets of IC designs for low-power applications. As IC designs are required to deliver increased performance and functionality while meeting reduced power and price targets, designers must adopt a comprehensive RTL2Gate approach that treats power as a design goal from early stage to sign-off. Additionally, as designs migrate to lower supply voltages using advanced technology nodes (<28nm), dynamic power noise impact becomes even more significant. This presentation discusses PowerArtist, the industry's leading RTL design-for-power solution, and RedHawk, the industry-standard dynamic power sign-off platform, along with an RTL2Gate methodology for how these platforms can be used to meet complex and competing performance−power−price targets.

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Presentation

Keeping Up with Moore’s Law

From Dimensions of Electronic Design Seminar, 2012: Today’s mobile electronics demand tighter power budgets while delivering greater functionality and performance. Advancements in semiconductor technology aim to address these conflicting design targets. However, as chips migrate to sub-20nm process nodes or use stacked-die (3D-IC) technologies, the ability to model and accurately predict the power/ground noise and its impact on the IC’s performance and reliability become critical for success with advanced low-power designs. This track discusses tools and methodologies that address power and reliability challenges, along with real designer experiences: - Comprehensive RTL2Gate methodology with PowerArtist‘s market-leading RTL design-for-power solutions and RedHawk’s industry-standard platform for dynamic power sign-off - The latest generation of RedHawk architected for stacked-die/3D-IC design analysis with hierarchical dynamic simulation and multi-pane/multi-canvas GUI - Tools for addressing power noise reliability challenges, such as electromigration (EM) and electrostatic discharge (ESD), specifically at sub-20nm process nodes

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Presentation

Advanced Reliability with RedHawk, Totem, and PathFinder

From Dimensions of Electronic Design Seminar, 2012: Reliability checks for EM and ESD are becoming increasingly complex. As designs move to 28nm and beyond, power and signal line electromigration has become an even more critical design sign-off requirement. In addition, ESD failures can significantly degrade a part’s yield unless you use simulation methods that address HBM, CDM and MM checks. Reliability is a long-term effect that can alter the operation of a device through power noise and thermal impacts. This presentation reviews the evolution of reliability challenges for advanced technology nodes and offers a methodology for how to address these issues using Apache's comprehensive reliability modeling and simulation solutions for power and signal EM, full-chip ESD and thermal-stress integrity.

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Page  37 of 187    37 38 39 40 41