Layout Editor
ANSYS TPA includes an intuitive 2-D layout-based interface that allows engineers to create and modify package layouts and designs. TPA also has the ability to render geometry in 3-D with the integrated 3-D viewer.
The new 2-D layout editor and 3-D viewer enable:
- Creation of advanced wirebond or flip-chip designs from scratch or modification/correction of designs imported from third-party layout tools
- System-in-package (SiP) designs with multiple wirebond configurations including trace-to-trace, die-to-die and cascaded
- User-defined wirebond profiles expanding shapes from JEDEC 4- and 5-point to include arbitrary polylines
- Complex solder ball models that capture true shape and subsequent electrical performance of solder balls and flip-chip solder bumps
- Layer stack-up editing
- Via pad stack editing
- VB scripting support
- Performance of validation checks to verify setup, including detection of self-intersecting polygons; disjoint nets; overlapping (DC-shorted) nets, vias and bondwires; and illegal connections between bonding pads and bondwires