DAC 2017

Best Practices Seminars

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  Production Proven
  Workflows for ADAS,
  Mobile and HPC
  Designs

  The demanding requirements for next-generation automotive, mobile and high-performance computing applications require the use of 16nm and 7nm SoCs to deliver greater functionality and higher performance at a much lower cost. With time to market being a critical success factor for these designs, the cost of silicon failure is huge. In this presentation, you will learn about production-proven ANSYS workflows for chip, package and system design for ADAS, mobile and HPC designs.

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  Next Generation SoC
  Power Noise
  Reliability Signoff

  Learn how you can maximize design coverage and accelerate convergence for SoC power signoff using the latest ANSYS SeaScape platform. With unparalleled scalability across thousands of cores using big data techniques, ANSYS SeaScape helps you sign off billion-plus instance designs within a few hours on commodity hardware. You will also learn how you can leverage multivariable analytics to achieve significantly better signoff confidence and drive meaningful design optimization. ANSYS SeaScape machine learning technology automates time-consuming procedures by aggregating key insights across different designs using continuing and prior simulation data. Retool and rethink your design signoff strategy using the ANSYS SeaScape big data platform.

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  Thermal, EM and ESD
  Reliability Signoff for
  Advanced Designs

  This presentation highlights the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge (ESD) robustness in advanced SoCs. It also describes how these factors can be addressed in a systematic way using ANSYS reliability platforms. Come and learn how ANSYS thermal solutions offer comprehensive chip-package-system thermal analysis and thermal-aware EM signoff for FinFET designs. Learn how ANSYS PathFinder can help ensure ESD integrity from the IO/IP level to the SoC for HBM and CDM analysis. This session will also cover best practices for ESD model hand-off from IP to SoC for chip ESD validation, and from SoC to board for system-level ESD simulations.

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  Analog and Mixed-Signal
  IP Power Noise
  Reliability Signoff

  A robust and reliable IP is key to the success of SoCs. Power noise and reliability are major challenges that IP designers face today. The complexity of IP containing a mix of analog and digital content makes pure SPICE or fast SPICE-based validation approaches extremely challenging. An in-situ validation of IP is critical for successful integration of IP in SoCs. In this session, we will discuss how ANSYS solutions can provide an accurate, high-capacity, multimode validation platform that can natively analyze complex analog and mixed-signal (AMS) IPs for power-noise, EM, ESD and thermal issues. We will also discuss how IP designers can generate accurate power and reliability models to facilitate SoC integration and signoff.

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  Bridging the Gap of
  Chip, Package
  & System

  The existing margin-driven approach of independently validating the chip, package and board severely limits the ability to globally optimize these systems without overdesigning. This silo-based approach affects cost and schedule, and does not guarantee optimal system performance. This presentation will address the need for bridging this gap, and will highlight the requirements for chip-level power, signal, thermal and ESD models for accurate system-level simulations. You will also learn how the latest ANSYS chip model analyzer (CMA) platform can help perform AC and transient simulations for package and board analysis using a wide range of chip power models.

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  RTL-driven System
  Power Profiling &
  Reduction

  Designs competing on power have not only adopted but expanded RTL power methodologies. This session will focus on the best practices of low-power RTL design that are followed by semiconductor design companies to analyze, debug and reduce power. These practices include new use models of power profiling of system-level applications spanning hundreds of milliseconds to enable software-driven power optimization.

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  Variability-aware and
  SPICE-accurate
  Timing Closure

  There are many sources of on-chip variation that are conspiring to kill your project. Learn how the ANSYS FX platform with its unique variation-aware technology can save you from gross inaccuracies in your current methods of modeling variation. Important topics include SPICE accurate process variation, especially at low voltage; SPICE accurate voltage variation including clock jitter due to IR drop; and a methodology shift in modeling chip-level aging that is easier, faster and more accurate than current approaches.