Semiconductor designers focus on developing devices including BGAs, flip chips, MCMs, stack dies and lead frame packages. Engineers in this sector face a number of challenges — many of them multidisciplinary, centering on mechanical, thermal and electromagnetic. The driving force in the industry is the continuing need to reduce feature size: The latest processors use transistors with features of 28 nanometers or smaller. Thermally, this reduction results in increased power densities with higher junction temperatures and larger thermal variations across the die and package. In addition, package designers must deal with the increasing geometric complexities of newer package types such as MCMs and stack dies. Designs must include board and system-level effects.
In the mechanical discipline, nonlinear behaviors come into play in semiconductor design, including fatigue, delamination, creep, buckling and fracture. Engineers must also address increasing geometric complexity, nonlinear material properties, and multidisciplinary behaviors like thermomechanical stress or joule heating.
Increased governmental regulations complicate semiconductor design, with the expectation of greener manufacturing processes and lead-free semiconductor packages. In the electromagnetics arena, designers face increasing signal speeds and lower power consumption requirements, leading to more challenging power-and signal-integrity solutions as well as increasing incidents of electromagnetic interference within the high-speed channel.
To address these challenges, ANSYS provides a variety of multidisciplinary tools.
To rule out complications during the manufacturing process, you can use ANSYS Fluent software to simulate the wafer manufacturing process, including etching and cleaning, as well as package manufacturing, such as soldering SMTs and the package encapsulate reflow process.
ANSYS Icepak software enables detailed conduction, convection and radiation analysis on various package types, including impact of trace layout on thermal design. Joule heating data can be imported following an SI/PI simulation with the SIwave product. Engineers can optimize via design using ANSYS tools, identifying and resolving the effects of coating and underfill materials. Due to its adaptive architecture, the ANSYS suite interfaces with select industry partners’ tools, enabling integrated solutions that extend the functionality and efficiency of the simulation process. Relative to the semiconductor industry, ANSYS Icepak can import variable die power data from partner die-level design tools.
ANSYS Mechanical technology can be used to predict thermal, mechanical and moisture-driven stress and strain in a variety of package types. Semiconductor analysis with ANSYS tools often incorporates nonlinear behaviors, including package warpage, solder joint creep, fracture in through-silicon-via designs, fatigue and delimitation. ANSYS capabilities offer the ability to conduct drop and vibration analyses.
Courtesy of PADT.
ANSYS offers tools to create the next generation of DigitalRF CMOS ICs, GaAs/SiGe RFICs, and SIP/SOC designs. HFSS, SIwave, Q3D Extractor and DesignerSI provide a platform to design innovative circuit topologies that integrate digital, analog and RF functionality as well as new device and process technologies that drive optimization of size, power, cost and yield.
HFSS, Q3D Extractor, and SIwave are used to extract GHz accurate S-Parameter models, W-elements and Full-Wave SPICE models for on-chip interconnect and complete IC packages. In addition, these tools are dynamically linked to DesignerSI for high-speed circuit simulation and statistical analysis; and final verification of the IC with package and board parasitics included.
Remaining competitive in today’s semiconductor market means integrated circuit (IC) designers must employ a variety of specialized tools and tactics to quickly meet performance, power and price targets for their designs. Meeting these conflicting goals requires enlisting the use of advanced architectural and design techniques, including the latest three-dimensional IC (3D-IC) or stacked-die architectures — which can help to meet performance and power targets by extending integration capabilities beyond traditional system-on-chip (SoC) methodologies.
ANSYS subsidiary Apache Design provides innovative simulation-driven power analysis and optimization solutions and methodologies that enable IC designers to develop products that meet stringent power specifications. At the same time, the product can reliably and consistently deliver power to the entire system and mitigate failures caused by power-induced noise. A comprehensive suite of integrated software and methodologies addresses a full spectrum of power, noise and reliability challenges, offering power reduction, power integrity and signal integrity, thermal management, and EM, ESD and EMI verification, from early in the design phase through final system signoff.
Highly differentiated platforms address the unique challenges associated with various phases of IC and electronic system design processes, including RTL-level power budgeting (PowerArtist); IP power delivery integrity and power noise analysis (Totem); SoC power integrity validation and sign-off (RedHawk); IC package/board power, signal, and thermal integrity (Sentinel); and full-chip and IP-level ESD verification (PathFinder). Accurate and compact models enable RTL-to-silicon, analog-to-digital, and chip–package–system power methodologies that facilitate effective collaboration among multiple engineering teams and help to drive the electronic ecosystem.
PowerArtist is a register transfer language (RTL) power analysis and optimization platform that enables design teams to gain greater insight into IC power consumption at an early stage and allows implementation of various power optimization techniques. PowerArtist’s RTL Power Model (RPM) bridges the gap between RTL design and physical power integrity by enabling early power delivery network (PDN) and package prototyping, as well as signoff coverage for power integrity analysis.
RedHawk is a full-chip power integrity analysis and signoff platform for SoC designs. It ensures PDN quality to meet performance requirements and enables power grid validation and signoff for designs with respect to noise and reliability considerations.
Totem is a full-chip, layout-based power and noise platform for analog and mixed-signal designs. It addresses the challenges associated with global couplings of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise for memory components (Flash and DRAM), high-speed I/Os (HDMI and DDR), and analog circuits (power management ICs). Totem considers the impact of full-chip SoC substrate noise (CSE) by directly interfacing with RedHawk to obtain an accurate substrate injection signature for all digital components.
Sentinel is a complete chip–package–system (CPS) codesign/co-analysis solution addressing system-level power integrity, I/O-SSO, thermal, and EMI challenges. It combines the chip’s core switching PDN, I/O subsystem, and IC package/PCB models and analysis in a single environment for accurate CPS convergence from early stage prototyping to sign-off.
PathFinder is a comprehensive layout-based electrostatic discharge (ESD) integrity solution targeted to address the increasing reliability challenges faced by nanometer designs. PathFinder’s integrated modeling, extraction and simulation capabilities enable automated and exhaustive analysis of the entire IC, highlighting design weaknesses that can be susceptible to failure caused by an ESD event.