CPS Co-design and Analysis for Ensuring Integrity and Reliability of Electronic Systems

February 1, 2017

1:30 PM - 4:30 PM (PST)


Hyatt Regency Santa Clara
Bayshore West Room
5101 Great America Pkwy
Santa Clara, CA 95054

Ravi Ravikumar

The performance of an electronic system largely depends on its immunity from power, signal and thermal noise. Since the components — chip, package and system (CPS) — are designed by different teams, and often from different companies, they end up being defined for pre-defined margins, which are not necessarily optimal parameters. In this workshop, ANSYS uses customer design examples to demonstrate an integrated co-design and analysis solution with accurate chip model generation for power, signal and thermal integrity analysis. Speakers from Seagate and Samsung will share their CPS design methodologies.