The Backbone of the IoT
The rapid growth of the Internet of Things (IoT) is generating a huge increase in internet traffic. Companies that deliver the ultrahigh-speed systems-on-chip (SoCs) for multiterabit networking equipment must provide the highest level of data integrity while meeting power, performance, bandwidth and cost requirements. The ANSYS semiconductor toolset enables ClariPhy to meet this challenge and deliver SoCs without additional fab spins.
As the Internet of Things (IoT) grows from six billion connected devices today to an estimated 20 billion by 2020, global data traffic is expected to increase nearly five-fold, passing a new milestone figure of two zettabytes by 2019.  (One zettabyte is equal to a billion terabytes.) ClariPhy engineers are delivering next-generation communication architectures fabricated on the most advanced technology process nodes to enable the fabric of networks across the globe to handle rapid increases in data traffic without compromising quality of service. For these state-of-the-art designs to meet stringent performance and quality (reliability) requirements, the power delivered to the transistors inside these ultralarge system-on-chip (SoC) designs has to be robust across the chip and across all operating conditions. To meet these specifications, the global power distribution network (PDN) must be constructed with awareness of requirements on the chip (e.g., voltage drop, routing resources), the package (e.g., package plane, decaps) and the PCB (e.g., voltage regulator module placement).
In the past, ClariPhy engineers were able to simulate the PDN on the chip but could not accurately account for package effects or analyze the segments and components that comprise the package. With the reduced margins of the most advanced process nodes used today, PDN problems rooted in the package could necessitate an extra foundry spin, which could potentially delay delivery of the chip by a year.
Today, ClariPhy engineers use the ANSYS semiconductor design toolset to simultaneously model and analyze power– noise coupling across the chip as well as the package. They can now make intelligent trade-offs to manage the noise at the chip and package levels from the early stages of the design process. This makes it possible to deliver new products within a time window that enables success in the market.
POWER DISTRIBUTION NETWORK DESIGN CHALLENGES
Each chip typically has a maximum dynamic voltage drop that must be maintained through the circuit in all modes of operation. With the continuing adoption of lower on-chip supply voltages in modern semiconductor devices, circuits are becoming very sensitive to power supply noise. As margins for proper functionality decrease, just several millivolts of noise on the power rail can make the difference between a logic 1 and a logic 0, and potentially corrupt the data transmission. But, before the power even reaches the die, the system experiences a voltage drop at the chip–package interface. Static IR drop plays a role, but simulating time-dependent dynamic voltage drop, impacted by passive elements such as package inductance and decoupling capacitors, is even more important. With the number of transistors per square millimeter doubling with each product generation, the amount of current and number of signals in this small area also tends to double. This makes it increasingly difficult to supply sufficient voltage to every transistor on the chip under all possible operating conditions to avoid a dropped bit that could translate to a data transmission error.
Previously, separate chip and package teams worked in silos, relying upon upfront, project-wide decisions on specifications to guide their design on the chip. ClariPhy chip engineers simulated the voltage delivered across the chip and the resulting drop in voltage. But they had no way to accurately determine the value of voltage that was conveyed to the chip from the package, which in many cases had already been reduced, primarily due to the inductive effects of the package. This approach sufficed for previous technologies with generous design margins, but it will simply not work for the latest generation of products. The new designs are so intricate that if the first sample comes back from the foundry with PDN noise problems, it could easily take a year to fix, drastically reducing the revenue generated by the product.
"Engineers can better understand the complex interactions between the chip, package and PCB, and address these issues early in the design cycle."
CO-SIMULATION OF CHIP AND PACKAGE
ClariPhy switched to ANSYS tools a few years ago because of the software’s unique ability to incorporate the chip and package into a single simulation, enabling engineers to accurately determine dynamic voltage drop with package effects included, and to troubleshoot PDN noise problems all the way upstream to the source. Engineers use ANSYS RedHawk chip package analysis (CPA) to import the package layout and bump location file and automatically connect the bump locations on the chip to the package pins on the layout. RedHawk-CPA generates a 3-D finite element model to extract the high resolution (per-bump) physical RLCk parasitics of the package. Finally, the voltage sources are assigned and a package model is generated for use in RedHawk.
A recent chip–package co-simulation showed that voltage drop on the metal 1 layer (the lowest metal layer that interfaces with the silicon) closely matched the bump voltage map (at the interface between the package and die), indicating that the majority of the voltage drop occurred within the package. ClariPhy engineers added probe points across three different package locations on all 10 package layers. The voltage probes showed a large drop across the package core. Engineers then reduced the core height and re-ran the simulation. They discovered that effective inductance was reduced between 20 percent and 30 percent in seven key domains. This reduction in effective inductance manifested itself in improved chip power integrity, with lower dynamic voltage drops seen across the chip.
In another example, ClariPhy engineers evaluated the impact of merging power domains that were isolated at the chip as well as the package to supply adjacent blocks. Edits were quickly made in RedHawk-CPA to merge the domains and re-extract the package models. The dynamic voltage drops were substantially lower in the merged domains. In a third case, ClariPhy engineers noticed that multiple instantiations of the same block, each of which was sinking the same power through the same power grid architecture, had very different voltage drops. They looked at the pin RL maps in RedHawk-CPA and determined that the packaging accounted for nearly the entire difference in voltage drops among identical blocks. They proceeded to set probes within the package to zero in on the root cause.
GETTING THE DESIGN RIGHT THE FIRST TIME
RedHawk-CPA enabled collaboration across ClariPhy chip, package and system teams throughout the design of the CL20010 LightSpeed-II™ 200G coherent optical transport solution, which has 5 billion transistors and over 200 million gates. ClariPhy engineers used chip–package co-analysis to identify problems and provide timely information to the package team during the course of the project to help them make necessary edits. These edits were then used to update the chip simulation to ultimately mitigate package-induced voltage drops on the chip. Furthermore, co-designing the two interdependent components prevented overdesign and opened up previously unforeseen opportunities for cost savings.
The new chip was awarded a perfect 5.0 score in the 2016 Lightwave Innovation Reviews program. One of the judges commented: “This 200G Coherent SoC [system on chip], is truly groundbreaking, breathtaking and revolutionary, and ushers in an entire new era in optical communications.”
Equally as important as enabling the package and system effects when analyzing the chip, it is critical to take the chip and package effects into account when analyzing the system. The ability to generate a chip power model (CPM) from RedHawk with a direct link into ANSYS SIwave enables ClariPhy PCB/ system engineers to analyze the PDN of their reference boards, which in turn helps customers design their systems using ClariPhy chips.
Chip development can be a two-year process, and in the highly competitive semiconductor industry, reducing time-to-market is crucial for success. A spin could take a year, and during that time the market window could close. Issues with bugs and noise could destroy a return on a research-and-development investment. ANSYS tools allow early trade-offs to avoid bugs and noise long before fabrication. Simulation helps ClariPhy to ensure first-pass success and avoid prohibitive fab costs.
Using the ANSYS chip–package–system workflow enabled ClariPhy engineers to better understand the complex interactions between the chip, package and PCB, and to address these issues early in the design cycle to reduce development cost and deliver better products to market quickly.
 Cisco Visual Networking Index: Forecast and Methodology, 2014-2019 White Paper, www.cisco.com/c/en/us/solutions/collateral/service-provider/ip-ngn-ip-next-generationnetwork/ white_paper_c11-481360.html
 ClariPhy LightSpeed-II CL20010 Coherent SoC, www.lightwaveonline.com/ articles/2016-innovation-reviews/clariphy-lightspeed-ii-cl20010-coherent-soc.html